Method for straining a semiconductor wafer and a wafer substrate unit used therein

ABSTRACT

The present invention provides a method for straining a semiconductor wafer, the method comprising: providing a semiconductor wafer, the semiconductor wafer having a first wafer surface and a second wafer surface arranged substantially opposite the first wafer surface; providing a substrate, the substrate having a substrate surface; adhering the first wafer surface to the substrate surface, thereby connecting the semiconductor wafer to the substrate and forming a wafer substrate unit; heating the semiconductor wafer and the substrate to a first temperature; and cooling the wafer substrate unit to a second temperature lower than the first temperature; thereby straining and bending the semiconductor wafer. The present invention further provides a wafer substrate unit.

The present invention relates generally to the fabrication ofmicroelectronic devices, more particularly to a method for straining asemiconductor wafer, and to a wafer substrate unit.

BACKGROUND OF THE INVENTION

Mechanical stress engineering in the channel region of metal-oxidesemiconductor field-effect transistors (MOSFETs) has attracted muchattention to improve the drive current in the MOSFET devices.

Several techniques have been proposed based on engineering of thesubstrate, e.g., strain-Si/Si_(1-x)Ge_(x) (compare: Hoyt J. L. et al:“Strained silicon MOSFET technology” in IEDM Tech. Dig., 2002, pp. 23 to26; Takagi S. et al: “Channel structure design fabrication and carriertransport properties of strained Si/SiGe-on-insulator (strained SOI)MOSFETs” in IEDM Tech. Dig., 2003, pp. 57 to 60; Wang H. C. H. et al.:“Substrate-strained Silicon technology: Process integration” in IEDMTech. Dig., 2003, pp. 61 to 64; and Jung J. et al: “Tradeoff betweenmobility and subthreshold characteristics in dual-channelheterostructure n-and p-MOSFETs” in IEEE Electron Device Lett., vol. 25,no. 8, 2004, pp. 562 to 564).

Other available techniques are based on engineering of theshallow-trench-isolation (compare: Matsumoto T. et al.: “Novel SOI waferengineering using low stress and high mobility CMOSFET with <100>channel for embedded RF/analog applications” in IEDM Tech. Dig., 2002,pp. 663 to 666) and based on engineering of the gate electrodes(compare: Lu T. Y. et al: “Mobility enhancement in local strain channelnMOSFETs by stacked a-Si/Poly Si gate and capping nitride” in IEEEElectron Device Lett., vol. 26, no. 4, 2005, pp. 267 to 269; and DuriezB. et al.: “Gate stack optimization for 65 nm CMOS low power and highperformance platform” in IEDM Tech. Dig., 2004, pp. 847 to 850).

Yet another known technique is based on engineering of anetch-stop-layer, e.g., tensile Si₃N₄ (compare: Shimizu A. et al.: “Localmechanical-stress control (LMC): A new technique for CMOS-performanceenhancement” in IEDM Tech. Dig., 2001, pp. 433 to 436; Pidin S. et al.:“A novel strain enhanced CMOS architecture using selectively depositedhigh tensile and high compressive silicon nitride films” in IEDM Tech.Dig., 2004, pp. 213 to 216; Chen C. H. et al: “Stress memorizationTechnique (SMT) by selectively strained-nitride capping for sub-65 nmhigh-performance strained-Si device application” in VLSI Symp. Tech.Dig., 2004, pp. 56 and 57; and Ota K. et al: “Novel locally strainedchannel technique for high performance 55 nm CMOS” in IEDM Tech. Dig.,2002, pp. 27 to 30).

Yet another approach is based on engineering of Si_(1-x)Ge_(x) orSi_(1-x)C_(x) source/drain as side-stressors (compare: Ghani T. et al.:“A 90 nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors” in IEDM Tech. Dig.,2003, pp. 978 to 980; and Ang K. W et al.: “Enhanced performance in 50nm N-MOSFETs with silicon-carbon source/drain regions” in IEDM Tech.Dig., 2004, pp. 1069 to 1071), and based on engineering of somecombinations thereof (compare: Ge C. H. et al.: “Process-strained Si(PSS) CMOS technology featuring 3-D strain engineering” in IEDM Tech.Dig., 2003, pp. 73 to 76).

Recently, techniques of post-backend applied strain have been proposed(compare: Belford R. E. et al.: “Performance-augmented CMOS usingBackend uniaxial strain” in Proc. IEEE 60^(th) Dev. Res. Conf., 2002,pp. 41 and 42; Uchida K. et al.: “Experimental study of biaxial anduniaxial Strain effects on carrier mobility in bulk and ultrathin-bodySCI MOSFETs” in IEDM Tech. Dig., 2004, p. 229; and Maikap S. et al.:“Mechanically strained strained-Si NMOSFETs” in IEEE Electron DeviceLett., voL 25, no. 1, 2004, pp. 40 to 42). Although the stress wasapplied as late as the packaging step on diced samples, the improvementwas evident (e.g., as high as about 20% increase in hole mobility). U.S.Pat. No. 6,514,836 discloses a method of producing strainedmicroelectronic devices. Microelectronic devices can either be formedwithin a membrane, prior to straining or processed after straining. Themethod includes the steps of straining a membrane along at least oneaxis and hard pressing onto curved structures. Such techniques areadvantageous, as there is no need for alteration of standard CMOSfront-end integration and there is a potential for additionalenhancement even on a device with pre-built-in stress.

Nevertheless, the above mentioned techniques were limited to individualdie level either by pressing over a curved substrate, or“end”-/center-displaced point-bending methods. Particularly thepoint-bending methods may induce problems of non-uniform stressdistribution because of the localized mechanical forces applied.

It is a task of further research in microelectronic engineering to findways to add further functions to and to improve the performance offuture IC microelectronic devices with new materials and devicestructures since the scaling of traditional field-effect transistorsslows down. In particular, gate control over the channel should beretained, OFF-state drain-source leakage should be minimized,mobility/injection velocity of charge carriers should be improved, drivecurrent for low intrinsic delay should be improved, extrinsic resistanceshould be reduced, and power consumption should be reduced. Accordingly,it is a challenge to improve the electronic properties ofmicroelectronic devices. A first approach is described in Bera et al.:“The impact of uniform strain applied via bonding onto plastic substrateon MOSFET performance” in IEEE Electron Device Letters, vol 27, no. 1,January 2006.

Therefore, an objective of the present invention is to overcome thedrawbacks of the above mentioned prior art, and in particular to presenta method for providing uniform post-backend stress applied at the waferlevel, and to simplify the application of stress to the wafer.

SUMMARY OF THE INVENTION

According to an aspect of the present invention, a method for straininga semiconductor wafer, the method comprising: providing a semiconductorwafer, the semiconductor wafer having a first wafer surface and a secondwafer surface arranged substantially opposite the first wafer surface;providing a substrate, the substrate having a substrate surface;adhering the first wafer surface to the substrate surface, therebyconnecting the semiconductor wafer to the substrate and forming a wafersubstrate unit; heating the semiconductor wafer and the substrate to afirst temperature; and cooling the wafer substrate unit to a secondtemperature lower than the first temperature; thereby straining andbending the semiconductor wafer. The first wafer surface of thesemiconductor wafer is usually the backside of the semiconductor waferand the second wafer surface of the semiconductor wafer is usually thesurface of the semiconductor wafer where integrated circuits are built.

According to another aspect of the present invention, a wafer substrateunit comprises a semiconductor wafer and a substrate, wherein: thesemiconductor wafer has a first wafer surface, a second wafer surfacearranged substantially opposite the first wafer surface; the substratehas a substrate surface; the first wafer surface is adhered to thesubstrate surface such that the semiconductor wafer is connected to thesubstrate; and the substrate strains the semiconductor wafer such thatthe semiconductor wafer is bent. The following remarks regarding themethod of the present invention are also valid for this wafer substrateunit.

Some of the advantages provided by the method according to the presentinvention are as follows. First, this method can easily and simply beimplemented into the backend fabrication process of IC microelectronicdevices with a minimal number of process steps. Second, the performance(e.g., the mobility of charge carriers like electrons and holes) ofthese microelectronic devices processed according to the method of thisinvention can be improved. Third, this improvement of the performance ofthe microelectronic devices is uniform across the whole semiconductorwafer. Due to the minimal number of process steps needed to perform themethod of the present invention, the production costs forcorrespondingly produced microelectronic devices are lower than in theprior art. In particular, the present invention provides bending of thesemiconductor wafer and the strain applied for bending can be tuneddirectional and with respect to the magnitude as required.

Contrary to the prior art where at the backend of the fabrication theapplication of stress to a wafer is minimized for avoiding wafercracking, the present invention deliberately induces strain onto thesemiconductor wafer by the substrate to obtain a bent semiconductorwafer, and, thus, to improve charge carrier mobility in the channelbetween source and drain. Consequently, the present invention improvesthe electrical properties of IC microelectronic devices arranged on thesemiconductor wafer processed according to the method of the presentinvention.

It is pointed out that the substrate used in the method according to thepresent invention acts as strainer onto the semiconductor wafer and,thus, onto each of the microelectronic devices. During separation of themicroelectronic devices, the substrate is also separated into substrateparts. Therefore, after separation of the microelectronic devices, eachsubstrate part is connected to one of the microelectronic devices andstill strains this microelectronic device. In one embodiment, theresultant semiconductor wafer is dependent on the initial strain on thesubstrate. Depending on whether the initial strain on the substrate istensile or compressive, the resultant semiconductor wafer after bondingcan also be tensile or compressive strained.

In another embodiment, the semiconductor wafer and the substrate havedifferent thermal expansion coefficients. The semiconductor wafer has afirst thermal expansion coefficient and the substrate has a secondthermal expansion coefficient. Depending on whether the second thermalexpansion coefficient is greater than the first thermal expansioncoefficient or vice versa, the semiconductor wafer can be tensilestrained or compressive strained. Therefore, the method of the presentapplication may further comprise using materials for the semiconductorwafer and the substrate such that the second thermal expansioncoefficient is greater than the first thermal expansion coefficient orvice versa. Further, according to the present invention the substratemay strain the semiconductor wafer across the whole first wafer surfaceof the semiconductor wafer in an uniaxial direction or even in a biaxialdirection.

The semiconductor wafer may be formed of any suitable semiconductormaterials, such as silicon (Si), poly-silicon, gallium arsenide (GaAs),germanium (Ge) or silicon-germanium (SiGe). The substrate may be formedof any suitable material that can be adhered and while bending inducesstrain. In exemplary embodiments, such a material may be selected fromglass, fiberglass (FR-4), a laminate of glass reinforced hydrocarbon andceramic (such as “RO4***” series that are available from RogerCorporation, Connecticut, U.S.A.), polymeric material such aspolytetrafluoroethylene (PTFE), silicon nitride (Si₃N₄), titaniumnitride (TiN) or aluminum (Al), to name only a few suitable substratematerials. The substrate materials may be tensile strained orcompressive strained by nature but can also vary with the manner ofdeposition or treatment. As an illustrative example in this regard,silicon nitride (Si₃N₄) can be tensile or compressive depending on themanner of deposition and deposition conditions. Typical plasma-enhancedchemical vapor deposition (PECVD) Si₃N₄ is based on low-frequencybiasing power. The higher the biasing power means that a higher field isapplied onto the ions. This can cause a higher bombardment of ions onthe Si₃N₄ film and result in the Si₃N₄ film becoming more dense orcompressive. Reducing the biasing power can thereby result in the Si₃N₄film becoming less dense or tensile. As another illustrative example inthis regard, plasma vapor deposition (PVD) TiN can also be renderedtensile or compressive depending on the manner of deposition anddeposition conditions. The higher the temperature during deposition, themore tensile TiN becomes. For a further example of a tensile materialthat may be used here is aluminum (Al), which can either be deposited onor aligned with the semiconductor wafer.

Further, the semiconductor wafer may be provided with a diameter ofbetween about 20.32 cm (8 inches) to 30.38 cm (12 inches) and may have aparticular diameter of 20.32 cm (8 inches) and 30.38 cm (12 inches)respectively. Of course, semiconductor wafers of any other suitabledimensions, for example 4 inches or 6 inches can also be used. Thesemiconductor wafer can be a silicon wafer or Silicon on Insulator (SOI)wafer, but not so limited.

According to one embodiment of the present invention, the semiconductorwafer and the substrate may be heated individually to a firsttemperature. After the semiconductor wafer and the substrate have beenheated to the first temperature, the first wafer surface of thesemiconductor wafer is adhered to the substrate surface by bonding. Forthis purpose, the semiconductor wafer and the substrate can be heated toany suitable temperature at any suitable rate of heating depending onthe chosen material for the semiconductor wafer and the substrate. Forexample, this bonding is carried out after raising the temperature ofthe semiconductor wafer and of the substrate, for example FR-4 byheating at a heating rate of about 1° C. per minute to a value withinthe range of about 120° C. to 400° C., in particular to about 160° C.This temperature can then be maintained for any suitable time period ofabout 10 minutes to 40 minutes, such as about 20 minutes. The firstwafer surface is bonded to the substrate surface by applying a suitablepressure force of for example, about 0.064 MPa for a suitable timeperiod. This time period can be about 50 minutes. After applying thepressure force, the temperature is further maintained for a suitabletime period of about 10 minutes to 40 minutes, such as for about 20minutes. Then, the obtained wafer substrate unit is actively cooled at asuitable cooling rate of about 1° C. per minute down to a secondtemperature of about 50° C., before the wafer substrate unit passivelycools down to ambient temperature. Ambient temperature can be about 15°C. to about 25° C. or to about 40° C. but any suitable temperature canalso be used. In this respect it is noted that the formulation “activecooling” has the meaning of cooling by applying an external coolingmeans to the wafer substrate unit, and that the formulation “passivecooling” has the meaning of internal cooling by exposing the wafersubstrate unit to the ambient such that the temperature of the wafersubstrate unit over time converges to the ambient temperature. Therespective heating and cooling protocol can be determined empirically.The process conditions can be optimized according to the selectedmaterials and is not so limited.

In another embodiment, the semiconductor wafer and the substrate can bebonded together to form a wafer substrate unit before heating to a firsttemperature. A suitable pressure force is then applied to the wafersubstrate unit for a suitable time period. After applying the pressureforce, the temperature is maintained for a further suitable time periodbefore being cooled at a suitable cooling rate to a suitable secondtemperature. In this regard, it does not matter if the semiconductorwafer and substrate is being heated individually or heated after theyhave been bonded. All the temperatures and durations of heating andcooling can be interpreted by a person skilled in the art.

According to another embodiment of the present invention, the substrateis provided together with adhering the first wafer surface to thesubstrate surface in a single step by commonly depositing substratematerial onto the first wafer surface. The substrate material may bedeposited onto the first wafer surface by chemical vapor deposition(CVD) or by sputtering. In one embodiment, the substrate material isdeposited by PECVD. For FR-4 substrate material, the substrate materialdeposition may be carried out after raising the temperature of thesemiconductor wafer to a suitable temperature by heating at a suitableheating rate, for example by heating at about 1° C. per minute to avalue within the range of about 120° C. and 400° C., in particular ofabout 160° C. For Si₃N₄ or TiN substrate material, the temperature canbe raised to a value within the range of about 200° C. and 400° C. Thetemperature can then be maintained for a suitable period of time, suchas about 1 minute to about 30 minutes, for example about 20 minutes butis not so limited thereto. The heated first wafer surface is thencovered with heated substrate material. After deposition of thesubstrate material, the temperature may be maintained for a further 20minutes but not so limited. Then, the obtained wafer substrate unit maybe actively cooled at a cooling rate of for example about 1° C. perminute down to a temperature of about 50° C. Thereafter, the wafersubstrate unit passively cools down to about ambient temperature.

According to the present invention, the semiconductor wafer comprises aplurality of microelectronic devices at the second wafer surface of thesemiconductor wafer. These microelectronic devices may comprisemetal-oxide semiconductor field-effect transistors, i.e. at least oneN-MOSFET and/or P-MOSFET. Each metal-oxide semiconductor field-effecttransistor comprises a source, a drain and a gate, wherein the gate isarranged between the source and the drain. The semiconductor wafer isstrained either in a direction perpendicular to source-drain or in adirection parallel to gate or a combination thereof. The semiconductorwafer may also comprise a plurality of optoelectronics devices. Thebehavior of the optoelectronic devices on the semiconductor wafer canalso be modulated by the method of straining the semiconductor wafer.

In one embodiment, the semiconductor wafer can be thinned beforestraining the semiconductor wafer. In one illustrative embodiment, thesemiconductor wafer can be thinned to any suitable thickness of betweenbut not limited to 100 μm to 400 μm, for example to a thickness of about200 μm. The thinning of the semiconductor wafer can be performed by anysuitable process such as but not limited to mechanical grinding,chemical mechanical polishing (CMP), wet etching and atmosphericdownstream plasma (ADP) dry chemical etching (DCE).

In one embodiment of the method of the present invention, the substrateis patterned at the substrate surface before the semiconductor wafer isadhered to the substrate. The substrate can be wet-etched afterproduction of the substrate, or shadow masked during the production ofthe substrate. For example, shadow masking during the production of thesubstrate may be carried out by sputtering substrate material through ashadow mask. For adjusting the density of the substrate material and,thus, for obtaining a tensile strained substrate or a compressivestrained substrate, the substrate material can be sputtered at differentpowers. Further, the substrate may be patterned by one- ortwo-dimensionally patterning the substrate stripe alike.

The present invention as shortly described above will be more fullyunderstood and further features and advantages of the present inventionwill become clear in view of the following description, drawings andnon-limiting examples.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to understand the present invention and to demonstrate how thepresent invention may be carried out in practice, illustrativeembodiments will now be described by way of non-limiting examples only,with reference to the accompanying drawings. Therein, like referencenumerals denote like objects. In the accompanying drawings:

FIG. 1 shows a cross-section through a wafer substrate unit produced bya method according to a first embodiment of the present invention,wherein a semiconductor wafer comprising three microelectronic devicesis strained by a substrate;

FIG. 2 a shows a first step of the method for straining the wafersubstrate unit according to the first embodiment of the presentinvention;

FIG. 2 b shows a second step of the method for straining the wafersubstrate unit according to the first embodiment of the presentinvention;

FIG. 2 c shows a third step of the method for straining the wafersubstrate unit according to the first embodiment of the presentinvention;

FIG. 2 d shows a fourth step of the method for straining the wafersubstrate unit according to the first embodiment of the presentinvention together with an enlarged part of the final wafer substrateunit;

FIG. 3 a shows a cross-section through a wafer substrate unit duringproduction by a method according to a second embodiment of the presentinvention, wherein a semiconductor wafer comprising threemicroelectronic devices is covered by a substrate;

FIG. 3 b shows an enlarged cross-section through the wafer substrateunit produced by the method according to the second embodiment of thepresent invention;

FIG. 4 a shows a photograph of a wafer substrate unit produced by themethod according to the first or second embodiment of the presentinvention and strained in horizontal direction;

FIG. 4 b shows a photograph of a wafer substrate unit produced by themethod according to the first or second embodiment of the presentinvention and strained in vertical direction;

FIG. 5 shows a simulation of the warpage of a wafer substrate unitstrained according to the present invention;

FIG. 6 a shows a simulation of the strain contour of a wafer substrateunit strained according to the present invention;

FIG. 6 b shows a simulation of the stress contour of a wafer substrateunit strained according to the present invention;

FIG. 7 shows a photograph of a wafer substrate unit biaxially strainedaccording to the present invention;

FIG. 8 shows a schematic top view onto a microelectronic device arrangedon a wafer substrate unit strained according to the present invention;

FIG. 9 shows a diagram with two graphs of simulated strain, one graphbelonging to the values of a wafer substrate unit strained according tothe present invention and, for comparison, one graph belonging to thevalues of a wafer substrate unit strained according to the prior art;

FIG. 10 a shows a graphical diagram of drain current vs. drain voltagefor an N-MOSFET arranged on a wafer substrate unit according to thepresent invention with and without strain;

FIG. 10 b shows a graphical diagram of drain current vs. drain voltagefor a P-MOSFET arranged on a wafer substrate unit according to thepresent invention with and without strain;

FIG. 11 a shows a graphical diagram of improvement of saturated draincurrent vs. gate length for an N-MOSFET arranged on a wafer substrateunit strained according to the present invention;

FIG. 11 b shows a graphical diagram of improvement of saturated draincurrent vs. gate width for N-MOSFETs with two different gate lengthsarranged on a wafer substrate unit strained according to the presentinvention; and

FIG. 12 shows a graphical diagram of improvement of saturated draincurrent vs. position on the wafer for N-MOSFETs with two different gatelengths and widths arranged on a wafer substrate unit strained accordingto the present invention.

FIG. 13 a shows a graphical diagram of enhancement of saturated draincurrent vs. gate length for an P-MOSFET arranged on a wafer substrateunit strained according to the present invention;

FIG. 13 b shows a graphical diagram of enhancement of linear mode draincurrent vs. gate length for an P-MOSFET arranged on a wafer substrateunit strained according to the present invention;

FIG. 14 a shows a schematic top view of a semiconductor wafer patternedaccording to the present invention.

FIG. 14 b shows a schematic top view of a substrate patterned accordingto the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

A cross-section through a wafer substrate unit 100 at ambienttemperature (also referred to as “room temperature”) is shown in FIG. 1which has been produced by a method according to a first embodiment ofthe present invention. The wafer substrate unit 100 comprises asubstrate 110, a semiconductor wafer 120, and a plurality ofmicroelectronic devices 130. The substrate 110 comprises a substratesurface 111, and the semiconductor wafer 120 comprises a first wafersurface 121 and a second wafer surface 122 arranged opposite the firstwafer surface 121. The substrate 110 contacts the semiconductor wafer120 so that the substrate surface 111 and the first wafer surface 121are congruent. The plurality of microelectronic devices 130 is arrangedon the second wafer surface 122, i.e. on the opposite site of thesemiconductor wafer 120 with respect to the substrate 110. It ispreferred to use silicon (Si) as material for the semiconductor wafer120, and to use composite of a resin epoxy reinforced with a wovenfiberglass (FR-4) as material for the substrate 110. Therefore, thesemiconductor wafer 120 has a thermal expansion coefficient of about2.6×10⁻⁶ per ° C. and the substrate 110 has a thermal expansioncoefficient of about 15×10⁻⁶ per ° C. Nevertheless, any other suitablematerials can be used for the semiconductor wafer 120 and for thesubstrate 110. For example, a laminate of glass reinforced hydrocarbonand ceramic (generally known as “RO4***” series), polymeric materialsuch as polytetrafluoroethylene (PTFE, generally known as “Teflon”),silicon nitride (Si₃N₄), or titanium nitride (TiN) can be used asmaterial for the substrate 110. Further, the R04*** series highfrequency laminates like R04000, R04350 and R04003 are materialsmanufactured by Rogers Corporation, Connecticut, U.S.A. In this regard,however, any suitable laminates can also be used.

The wafer substrate unit 100 is strained in that the substrate 110 wascompressed by large shrinkage and is now under the influence ofcompressive strain as indicated by two arrows 112 facing each other,whereas the semiconductor wafer 120 stands under the influence oftensile strain as indicated by two arrows 123 oriented in oppositedirections. Therefore, the wafer substrate unit 100 is in a bentcondition. There exists a strain-neutral plane 124 between thecompressive strain part and the tensile strain part of the wafersubstrate unit 100, the strain-neutral plane 124 existing inside thesemiconductor wafer 120. In consequence, each of the plurality ofmicroelectronic devices 130 also stands under the influence of tensilestrain. It is preferred to use metal-oxide semiconductor field-effecttransistors (MOSFET) as microelectronic devices 130. However, the personskilled in the art will know that the microelectronic devices 130 arenot limited to MOSFETs, but can also comprise any other suitableintegrated circuits, e.g., optical modulators, Schottky-barriers,bipolar transistors, etc.

It has to be noted that the bending radius of the wafer substrate unit100 can be controlled via the thickness of the substrate 110.Preferably, the thickness of the substrate 110 is about 200 μm. Further,according to the present invention, the semiconductor wafer 120 has adiameter of about 20.32 cm (8 inches).

With respect to the composite material of resin epoxy reinforced with awoven fiberglass (FR-4) which is used for the substrate 110 in anillustrative example of the first embodiment of the present invention,it is noted that this material is an anisotropic material causingorthotropic elasticity. Due to the anisotropy of this material, theelastic modulus E, the Poisson's ratio ν, and the thermal expansioncoefficient ε are different in x-, y- and z-directions. This materialhas an elastic modulus in x- and y-directions of E_(x)=E_(y)=22 GPa andin z-direction of E_(z)=10 GPa, a thermal expansion coefficient inx-direction of TEC_(x)=15 ppm/° C., in y-direction of TEC_(y)=30 ppm/°C., and in z-direction of TEC_(z)=70 ppm/° C., and a Poisson's ratio ofν_(xy)=ν_(yz)=0.28 and ν_(xz)=0.11. In this respect, the followingequation (1) is generally valid for this material:

ν_(ij)/E_(i)=ν_(ji)/E_(j).  (1)

The following equation (2) can be used for calculating the strain tensorε_(ij):

$\begin{matrix}{\begin{Bmatrix}ɛ_{xx} \\ɛ_{yy} \\ɛ_{zz} \\ɛ_{xy} \\ɛ_{xz} \\ɛ_{yz}\end{Bmatrix} = {\quad {\quad{\begin{bmatrix}{1/E_{x}} & {{- v_{yx}}/E_{y}} & {{- v_{zx}}/E_{z}} & 0 & 0 & 0 \\{{- v_{xy}}/E_{x}} & {1/E_{y}} & {{- v_{zy}}/E_{z}} & 0 & 0 & 0 \\{{- v_{xz}}/E_{1}} & {{- v_{yz}}/E_{2}} & {1/E_{z}} & 0 & 0 & 0 \\0 & 0 & 0 & {{1/2}\; G_{xy}} & 0 & 0 \\0 & 0 & 0 & 0 & {{1/2}\; G_{xz}} & 0 \\0 & 0 & 0 & 0 & 0 & {{1/2}\; G_{yz}}\end{bmatrix}{\begin{Bmatrix}\sigma_{xx} \\\sigma_{yy} \\\sigma_{zz} \\\sigma_{xy} \\\sigma_{xz} \\\sigma_{yz}\end{Bmatrix}.}}}}} & (2)\end{matrix}$

In the equation (2), σ_(ij) is the stress tensor, G_(ij) is the shearmodulus tensor, and ν_(ij) is the Poisson's ratio tensor, where i, j canbe any one of x, y or z.

In the following, a method for producing the strained wafersemiconductor unit 100, and therefore for straining the semiconductorwafer 120, according to a first embodiment of the present invention isdescribed in detail with respect to FIG. 2 a to FIG. 2 d.

The method according to the first embodiment of the present invention asillustrated in FIG. 2 a starts at ambient temperature with the substrate110 having the desired thickness and the semiconductor wafer 120 beingcompletely processed by commonly known microelectronic semiconductorprocessing techniques which are known to a person of average skilled inthe art. The dotted line 210 represents the active layer comprising themicroelectronic devices 130, e.g. transistors, integrated at thesemiconductor wafer 120. Besides the active layer 210, the semiconductorwafer 120 may comprise further layers, e.g., connection layerscomprising interconnects and track conductors.

According to the illustrative example of the method of the firstembodiment of the present invention in FIG. 2 b, the substrate 110 andthe semiconductor wafer 120 together with the microelectronic devices130 are heated at a heating rate of about 1° C. per minute to atemperature of about 160° C. If necessary, the heating may also reachtemperatures up to about 200° C. This temperature is maintained forabout 20 minutes. During this heating and maintaining of thistemperature, the substrate 110 and the semiconductor wafer 120 expand.In one illustrative example, the substrate 110 has a thermal expansioncoefficient which is greater than the thermal expansion coefficient ofthe semiconductor wafer 120; therefore the substrate 110 expands morethan the semiconductor wafer 120. FIG. 2 b shows a step of the methodaccording to the first embodiment of the present invention where theexpanded semiconductor wafer 120 is loosely adhered to the expandedsubstrate 110. The expansion of the substrate 110 is indicated by thesubstrate expansion arrows 211, and the expansion of the semiconductorwafer 120 is indicated by the wafer expansion arrows 212. Since theexpansion of the substrate 110 is greater than that of the semiconductorwafer 120, the substrate expansion arrows 211 are shown bigger than thewafer expansion arrows 212.

Next, in this illustrative example in FIG. 2 c, the expandedsemiconductor wafer 120 is adhered by means of a pressure force of about0.064 MPa to the expanded substrate 110. The pressure force is appliedfor about 50 minutes at the above mentioned temperature of about 160° C.In particular, the first wafer surface 121 is adhered to the substratesurface 111. By applying this pressure force under the given conditions,the expanded semiconductor wafer 120 is bonded to the expanded substrate110 and forms an expanded wafer substrate unit 220. The situation duringand shortly after this bonding is shown in FIG. 2 c. Therein, thesubstrate expansion arrows 211 and the wafer expansion arrows 212 arestill shown since the expanded wafer substrate unit 220 is still in itsheated condition. After removal of the pressure force, the temperatureof about 160° C. is maintained for further 20 minutes on the expandedwafer substrate unit 220.

After these further 20 minutes, the temperature is actively cooled downin the illustrative example in FIG. 2 d at a cooling rate of about 1° C.per minute to a temperature of about 50° C. During this cooling step,the expanded wafer substrate unit 220 contracts. Due to the differentthermal expansion coefficients, the substrate 110 contracts more thanthe semiconductor wafer 120 leading to stress inside the wafer substrateunit 220. This different contraction is expressed by substratecontraction arrows 213 and wafer contraction arrows 214 having adifferent size in FIG. 2 d. The stress inside the wafer substrate unit220 results in compression strain in the substrate 110 and in tensilestrain in the semiconductor wafer 120 leading to a bending of the wafersubstrate unit 220. However in another illustrative embodiment, thebending of the wafer substrate unit 220 can also be due to the initialstrain on the substrate 110 rather than due to the different thermalexpansion coefficients.

After this active cooling of the wafer substrate unit 220 down to atemperature of about 50° C., the wafer substrate unit 220 furtherpassively cools down by itself to ambient temperature. The cooled downfinal wafer substrate unit 220 together with an enlarged part 250 of thefinal wafer substrate unit 220 are shown in FIG. 2 d. It is noted thatthe bending effect onto the wafer substrate unit 220 is shown onlyqualitatively in FIG. 2 d, but not quantitatively and not true to scale.The real bending radius results at least from the difference in thethermal expansion coefficients of the materials used for the substrate110 and the semiconductor wafer 120, from the thickness of the substrate110, from the thickness of the semiconductor wafer 120 or from the typeof substrate used as the substrate can be strained. Since the wholesubstrate 110 and the whole semiconductor wafer 120 are affected by theabove described method of the first embodiment of the present invention,biaxial tensile strain can be achieved for the complete area where thesubstrate 110 is bonded to the semiconductor wafer 120.

A cross-section through a wafer substrate unit 300 during production byan illustrative example of the method according to a second embodimentof the present invention is shown in FIG. 3 a. This wafer substrate unit300 comprises a semiconductor wafer 120 having three microelectronicdevices 130 and being covered by a substrate 110′. After heating thesemiconductor wafer 120 to a temperature of about 160° C. in a similarmanner like in the example of the first embodiment of the presentinvention, the substrate 110′ has been formed directly on the heatedsemiconductor wafer 120 by plasma-enhanced chemical vapor depositionwhich is indicated by two deposition arrows 310. Due to the depositionprocess, the substrate 110′ in this embodiment may comprise siliconnitride (Si₃N₄) or titanium nitride (TiN). For depositing the substratematerial, the plasma-enhanced chemical vapor deposition is carried outat a current of between about 4 kA and about 8 kA. The heated wafersubstrate unit 300 is then cooled down to ambient temperature in amanner already described above with respect to the first embodiment ofthe present invention so that a description thereof is omitted here.

Like in the first embodiment of the present invention, also in theillustrative example of the second embodiment of the present invention,the initial strain on the substrate 110′ or the different thermalexpansion coefficients of the substrate 110′ and of the semiconductorwafer 120 result in stress affecting on the wafer substrate unit 300resulting in a bent wafer substrate unit 300. The stress level is tuned,e.g., by adjustment of the high-frequency bias power, of thetemperature, and/or of the sputtering power. An enlarged cross-sectionthrough the wafer substrate unit 300 produced by the method according tothe second embodiment of the present invention is shown in FIG. 3 b.When comparing FIG. 3 b and FIG. 2 d it can be seen that the final wafersubstrate units 100 and 300 are identical in their structure althoughthey have been produced differently. In the second embodiment of thepresent invention, the thickness of the substrate 110′ can be adjustedfor example, either by depositing a thicker substrate and, then,thinning this thicker substrate to the desired thickness, or bydepositing substrate material as much as necessary for the desiredthickness.

In both the first and second embodiment of the present invention, it ispossible to thin the semiconductor wafer 120 before combining it withthe substrate 110 or 110′ to the wafer substrate unit 100 or 300. Thisthinning is a commonly known process that is within the knowledge of theaverage skilled person skilled in the art.

If it is desired to only uniaxially strain the wafer substrate unit, thepresent invention provides the possibility to either use an additional,textured glue layer between the substrate and the semiconductor wafer ofthe first embodiment of the present invention. It is also possible totexture the substrate directly, i.e., to provide an appropriate pattern(e.g., a plurality of parallel lines like in an optical grating) to thewafer substrate unit. The present invention also provides thepossibility to make use of a textured shadow mask during depositingsubstrate material according to the second embodiment of the presentinvention. This texturing (of the glue layer, the substrate or theshadow mask) can be carried out by providing a stripe alike wraporiented mainly in one direction. If this texturing is carried out incross-hatch directions, the biaxial strain to the wafer substrate unitcan be enhanced. The texturing may result in cavities having a depth ofup to about 200 μm.

Wafer substrate units have been successfully built according to theinvention with the following data: thickness of the semiconductor waferin the range between about 170 μm and about 700 μm; N- and P-MOSFETswith a gate width of about 10 μm and gate lengths in the range of about10 μm to about 65 nm; thickness of the textured glue layer at about 60μm; thickness of the FR-4 substrate at about 0.1 mm, at about 0.4 mm,and at about 0.8 mm. A 0.2 mm thick R04003 substrate showed a moreuniform bending behavior than any of the FR-4 substrates.

FIG. 4 a and FIG. 4 b show photographs of two wafer substrate units 410and 420 produced by the method according to the first or secondembodiment of the present invention and strained in horizontal direction(FIG. 4 a) or in vertical direction (FIG. 4 b), wherein these directionsare related to the drawing plane (please note that the semiconductorwafers of both wafer substrate units are oriented identical in bothphotographs with respect to crystal orientation). As can be gatheredfrom FIG. 4 a and FIG. 4 b, the wafer substrate units 410 and 420 havebeen readily produced since microelectronic device structures can beseen in these figures.

A simulation of the warpage contour 500 of a wafer substrate unitstrained according to the present invention is shown in FIG. 5. Thiswarpage contour 500 is a result from the residual stress in the wafersubstrate unit due to grinding. The shown simulation gives a maximalvalue for the warpage contour 500 of 19.832 mm, whereas the maximalvalue of the warpage contour of the wafer substrate unit 420 as shown inFIG. 4 b has been measured to be 20 mm.

FIG. 6 a shows a simulation of the strain contour 610 and FIG. 6 b showsa simulation of the stress contour 620 both of a wafer substrate unitstrained according to the present invention. Accordingly, the straincontour 610 is uniform and homogeneous with a value of about 0.07%(“0.711E-03”), and the stress contour 620 shows also a uniform stressalong the warpage direction with a value of about 124 MPa (“0.124E+09”).On basis of such simulations, it has been found that thinning a normalsemiconductor wafer having a thickness of approximately 700 μm to athickness of about 200 μm will increase the value of the strain by about3 times.

A photograph of a wafer substrate unit 700 biaxially strained accordingto the present invention is shown in FIG. 7. The wafer substrate unit700 comprises a substrate 710 comprising fiberglass (FR-4) and adiameter of about 20.32 cm (8 inches). At the center, about one quarterof the substrate 710 is covered with a semiconductor wafer 720. As canbe gathered from FIG. 7, the wafer substrate unit 700 is uniformlybiaxially strained.

FIG. 8 shows a schematic top view onto a field-effect transistor 800used as microelectronic device and arranged on a wafer substrate unitstrained according to the present invention. The field-effect transistor800 comprises a source 810, a drain 820 and a gate 830. Further, two ofthree different straining directions (X and Y) are noted in FIG. 8. Inparticular, the X-direction is defined by a direction from source 810 todrain 820 or vice versa and named “source drain direction”, whereas theY-direction is defined by the longitudinal expansion of the gate 830width, i.e. the Y-direction is perpendicular to the X-direction andparallel to the gate 830 width in same plane. Not shown in FIG. 8 is theZ-direction, which is perpendicular to the X-Y plane. With respect toFIG. 4 a and FIG. 4 b it is noted that the horizontal straining of thewafer substrate unit 410 is shown in FIG. 4 a along the Y-direction andthat the vertical straining of the wafer substrate unit 420 is shown inFIG. 4 b along the X-direction.

Different directions have to be strained for different types offield-effect transistor 800 (C. Hu/VLSI Technology Symp., 2004). Theperformance of an N-MOSFET is enhanced by tensile straining in X- andY-directions and by compressive straining in Z-direction, whereas theperformance of a P-MOSFET is enhanced by tensile straining in Y- andZ-directions and by compressive straining in X-direction. Theserelations are shown for clarity in Table 1:

TABLE 1 Kind of Strain N-MOSFET P-MOSFET Strain Direction (NMOS) (PMOS)X-Direction tensile compressive Y-Direction tensile tensile Z-Directioncompressive tensile

In view of X- and Y-directions, tensile strain is needed in Y-directionfor both N- and P-MOSFETs, whereas for N-MOSFETs additionally tensilestrain in X-direction is needed. It is noted that no tensile strain inX-direction is needed for P-MOSFETs, but compressive strain is necessaryin X-direction for P-MOSFETs. In this respect it is also noted that iftwo orthogonal directions are tensile strained, the third orthogonaldirection must be compressive strained.

FIG. 9 shows a diagram 900 with two graphs of simulated strain tosemiconductor wafers having a diameter of about 180 mm. The strain graph901 indicated by triangles belongs to the values of a semiconductorwafer 120 strained according to the present invention and, forcomparison, the strain graph 902 indicated by circles belongs to thevalues of a semiconductor wafer 930 strained according to the prior art.The x-axis in diagram 900 gives the distance r from the center of therespective semiconductor wafer 120 or 930 in millimeters, the righty-axis gives the strain of the semiconductor wafer 930 strainedaccording to the prior art in percent, and the left y-axis gives thestrain of the semiconductor wafer 930 strained according to the presentinvention in percent. As already described above in connection with FIG.1, the wafer substrate unit 100 strained according to the presentinvention comprises a substrate 110 straining a semiconductor wafer 120causing tensile strain 123. The microelectronic devices arranged on therespective semiconductor wafer are not shown in FIG. 9 forsimplification. The semiconductor wafer 930 strained according to theprior art is mechanically strained by fixing the ends thereof inappropriate fixing devices 931, affecting the center of thesemiconductor wafer 930 with a straining force 932 such that the ends ofthe semiconductor wafer 930 are affected with an opposite strainingforce 933 (which causes point bending of the semiconductor wafer 930)and, consequently, causing simultaneously tensile strain 934 andcompressive strain 935 in the semiconductor wafer 930. As can begathered from the strain graph 902, the strain in the semiconductorwafer 930 according to the prior art continually varies from positivevalues (about 0.425%) at the center to negative values (about −0.125%)at the ends of the semiconductor wafer 930. Contrary thereto, the straingraph 901 shows uniform and constant tensile strain (about 0.026%) overthe whole semiconductor wafer 120 when strained according to the presentinvention.

Graphical diagrams of drain current vs. drain voltage curves for aMOSFET arranged on a wafer substrate unit 100 according to the presentinvention are shown in FIG. 10 a and FIG. 10 b. In particular, FIG. 10 arelates to an N-MOSFET and FIG. 10 b relates to a P-MOSFET. Bothgraphical diagrams show curves for each two cases, one time with tensilestrain mainly applied along Y-direction to the semiconductor wafer(“after strain”=broken lines) and one time without applying strain tothe semiconductor wafer (“fresh”=continuous lines). The drain current IDis plotted in μA per μm, and the drain voltage V_(D) is plotted in volt.The graphical diagrams in FIG. 10 a and FIG. 10 b are the result ofmeasurements for a gate length of L_(G)=0.3 μm and a gate width W=2 μmwith a variation in gate voltage V_(G) corrected with threshold voltageV_(T), i.e., V_(G)−V_(T)=±0.0 V, ±0.3 V, ±0.6 V, +0.9 V and ±1.2 V(positive values for N-MOSFET, negative values for P-MOSFET). As can begathered from FIG. 10 a and FIG. 10 b, straining results in anenhancement, i.e., increase, of the drain current by between about 8%and about 10%.

FIG. 11 a shows a graphical diagram of measured improvement of saturateddrain current vs. gate length for an N-MOSFET having a gate width W of20 μm and being arranged on a wafer substrate unit strained according tothe present invention. The improvement of saturated drain currentI_(DSAT) Improvement is plotted in percent, and the gate length L_(G) isplotted in μm. The measurement of I_(DSAT) Improvement has been carriedout at a voltage between drain and source V_(DS) of 1.2 V. It can begathered from FIG. 11 a that I_(DSAT) Improvement is very stable at avalue of about 10% for gate lengths in the range of between about 0.05μm and about 0.55 μm.

FIG. 11 b shows a graphical diagram of measured improvement of saturateddrain current vs. gate width for N-MOSFETs with gate lengths L_(G) of0.23 μm and 55 nm arranged on a wafer substrate unit strained accordingto the present invention. Like in FIG. 11 a, the improvement ofsaturated drain current I_(DSAT) Improvement is plotted in percent, andthe gate width W is plotted in μm. The measurement of I_(DSAT)Improvement has been carried out at a voltage between drain and sourceV_(DS) of 1.2 V. It can be gathered from FIG. 11 b that I_(DSAT)Improvement is also very stable at a value of about 9.5% for gate widthsin the range of between about 2 μm and about 20 μm. Therefore theimprovement of saturated drain current is free of dimensional dependencein either gate length or width.

A graphical diagram of measured improvement of saturated drain currentvs. position on the semiconductor wafer for two N-MOSFETs arranged on awafer substrate unit strained according to the present invention isshown in FIG. 12. The two N-MOSFETs have different gate lengths and gatewidths, in particular, one has a gate length L_(G) of 55 nm and a gatewidth W of 2 μm, whereas the other has a gate length L_(G) of 0.53 μmand a gate width W of 20 μm. The improvement of saturated drain currentI_(DSAT) Improvement is plotted in percent, and the position on thesemiconductor wafer is plotted in mm from the center at 0 mm to the edgeat 100 mm. As can be gathered from FIG. 12, the I_(DSAT) Improvement isuniform across the whole wafer, is independent of the gate length andwidth, and has a value of about 9.5%. An I_(DSAT) improvement of about7% is also observed for P-MOSFETs. Furthermore, the improvement iscompletely preserved in devices in individual dies after dicing.

FIG. 13 a shows a graphical diagram of enhancement of saturated draincurrent vs. gate length for a P-MOSFET with gate width W of 20 μm andbeing arranged on a wafer substrate unit strained according to thepresent invention. The enhancement of saturated drain current I_(DSAT)enhancement is plotted in percent, and the gate length L_(G) is plottedin μm. Similar to n-MOSFET in FIG. 11 a, the I_(DSAT) enhancement asgathered from FIG. 13 a is very stable at a value of about 8% for gatelengths in the range of between about 0.05 μm and about 4 μm.

FIG. 13 b shows a graphical diagram of enhancement of linear mode draincurrent vs. gate length for a P-MOSFET with gate length W of 20 μm andbeing arranged on a wafer substrate unit strained according to thepresent invention. The enhancement of linear mode drain current I_(DLIN)enhancement is plotted in percent, and the gate length L_(G) is plottedin μm. It can be gathered from FIG. 13 b that I_(DSAT) enhancement isvery stable at a value of about 11.5% for gate lengths in the range ofbetween about 0.05 μm and about 6 μm.

FIG. 14 a shows a schematic top view of a semiconductor wafer patternedon the backside or first wafer surface 121 of the semiconductor wafer120, where respective cavities or contact shapes 131 are made. The depthof the cavities are approximately about 200 μm. Preferential strain isinduced through different contact shapes with the substrate or bondingmaterial. Due to the patterned surface of the semiconductor backside,only certain areas will be bonded with the substrate material.Patterning can be used to engineered preferential strain on selectivedies.

FIG. 14 b shows a schematic top view of a substrate 110 patterned on thesubstrate surface 111, where respective cavities or contact shapes 132are made. The depth of the cavities is approximately about 200 μm.Similarly, preferential strain is induced through different contactshapes with the substrate or bonding material. Due to the patternedsurface of the semiconductor backside, only certain areas will be bondedwith the substrate material. Patterning can be used to engineeredpreferential strain on selective dies.

It should be mentioned that there exists also the possibility to coverthe interface of the semiconductor wafer, where the microelectronicdevices are integrated at, with substrate material for straining thesemiconductor wafer by the deposited substrate material (known as“topside coating”). For improvement of dissipation of heat generatedfrom the microelectronic devices during operation. The above described“backside coating” can be used, i.e. the adhering of the substrate(material) to the semiconductor wafer on an interface of thesemiconductor wafer which is opposite to the microelectronic devices.

The present invention can be further improved and made even morereliable by using substrate materials having larger thermal expansioncoefficients than the semiconductor wafer such as silicon nitride (SiN).Such an embodiment may be useful if a strained semiconductor wafer ofthe present invention is to be operated in a wide temperature range,e.g., from about −5° C. to about 125° C. as required for militaryapplication, for example.

Although this invention has been described in terms of illustrativeembodiments, it has to be understood that numerous variations andmodifications may be made, without departing from the spirit and scopeof this invention as set out in the following claims.

1. A method for straining a semiconductor wafer, the method comprising:providing a semiconductor wafer, the semiconductor wafer having a firstwafer surface and a second wafer surface arranged substantially oppositethe first wafer surface; providing a substrate, the substrate having asubstrate surface; adhering the first wafer surface to the substratesurface, thereby connecting the semiconductor wafer to the substrate andforming a wafer substrate unit; heating the semiconductor wafer and thesubstrate to a first temperature; and cooling the wafer substrate unitto a second temperature lower than the first temperature; therebystraining and bending the semiconductor wafer.
 2. The method of claim 1,further comprising providing the semiconductor wafer having a firstthermal expansion coefficient and providing the substrate having asecond thermal expansion coefficient.
 3. The method of claim 2, furthercomprising using materials for the semiconductor wafer and the substratesuch that the second thermal expansion coefficient is greater than thefirst thermal expansion coefficient.
 4. The method of claim 1, whereinadhering the first wafer surface to the substrate surface comprises thestep of bonding the first wafer surface onto the substrate surface. 5.The method of claim 1, wherein providing the substrate and adhering thefirst wafer surface to the substrate surface are carried out in a singlestep by depositing the substrate onto the first wafer surface.
 6. Themethod of claim 5, wherein depositing the substrate is carried out bychemical vapor deposition.
 7. The method of claim 6, wherein depositingthe substrate is carried out by plasma-enhanced chemical vapordeposition.
 8. The method of claim 5, wherein depositing the substrateis carried out by sputtering.
 9. The method of claim 1, wherein thesubstrate is tensile strained.
 10. The method of claim 1, wherein thesubstrate is compressive strained.
 11. The method of claim 1, whereinthe semiconductor wafer is strained uniaxially or biaxially.
 12. Themethod of claim 1, wherein the semiconductor wafer comprises a pluralityof microelectronic devices at the second wafer surface.
 13. The methodof claim 12, wherein the microelectronic devices comprises metal-oxidesemiconductor field-effect transistors.
 14. The method of claim 13,wherein the metal-oxide semiconductor field-effect transistors comprisesat least one N-MOSFET and/or one P-MOSFET.
 15. The method of claim 13,wherein each metal-oxide semiconductor field-effect transistor comprisesa source, a drain and a gate, wherein the gate is arranged between thesource and the drain.
 16. The method of claim 15, wherein the tensilestrain in the semiconductor wafer is in a direction perpendicular tosource-drain and parallel to gate.
 17. The method of claim 15, whereinthe tensile stain in the semiconductor wafer is in source-draindirection.
 18. The method of claim 1, wherein providing thesemiconductor wafer comprises thinning the semiconductor wafer.
 19. Themethod of claim 18, wherein thinning the semiconductor wafer comprisesthinning the semiconductor wafer to a thickness of about 200 μm.
 20. Themethod of claim 1, wherein providing the semiconductor wafer comprisesforming the semiconductor wafer out of a material selected from thegroup consisting of silicon, poly-silicon, gallium arsenide, germaniumand silicon-germanium.
 21. The method of claim 1, wherein providing thesemiconductor wafer comprises providing the semiconductor wafer with adiameter of between about 20.32 cm (8 inches) to about 30.48 cm (12inches).
 22. The method of claim 1, wherein the substrate comprises amaterial selected from the group consisting of fiberglass, laminatematerial, polymeric material, silicon nitride and titanium nitride. 23.The method of claim 1, wherein the first temperature is between about120° C. and about 400° C.
 24. The method of claim 23, wherein the firsttemperature is between about 160° C. and about 200° C.
 25. The method ofclaim 1, wherein the second temperature is about ambient temperature.26. The method of claim 1, wherein providing the substrate comprisespatterning the substrate at the substrate surface.
 27. The method ofclaim 26, wherein patterning the substrate comprises wet-etching thesubstrate after production of the substrate, or shadow masking duringthe production of the substrate.
 28. The method of claim 27, whereinshadow masking during the production of the substrate comprisessputtering substrate material through a shadow mask.
 29. The method ofclaim 28, wherein sputtering substrate material comprises sputtering thesubstrate material at different powers for adjusting material densityand, thus, for obtaining a tensile strained substrate or a compressivestrained substrate.
 30. The method of claim 26, wherein patterning thesubstrate comprises one- or two-dimensionally patterning the substratestripe alike.
 31. The method of claim 1, wherein providing thesemiconductor wafer comprises patterning the semiconductor wafer at thefirst wafer surface.
 32. A wafer substrate unit comprising asemiconductor wafer and a substrate, wherein: the semiconductor waferhas a first wafer surface, a second wafer surface arranged substantiallyopposite the first wafer surface; the substrate has a substrate surface;the first wafer surface is adhered to the substrate surface such thatthe semiconductor wafer is connected to the substrate; and the substratestrains the semiconductor wafer such that the semiconductor wafer isbent.
 33. The wafer substrate unit of claim 32, wherein the substratestrains the semiconductor wafer uniaxial or biaxial.
 34. The wafersubstrate unit of claim 32, wherein the substrate tensile strains thesemiconductor wafer.
 35. The wafer substrate unit of claim 32, whereinthe substrate compressive strains the semiconductor wafer.
 36. The wafersubstrate unit of claim 32, further comprising a plurality ofmicroelectronic devices at the second wafer surface of the semiconductorwafer.
 37. The wafer substrate unit of claim 36, wherein the pluralityof microelectronic devices comprises a plurality of metal-oxidesemiconductor field-effect transistors.
 38. The wafer substrate unit ofclaim 37, wherein the plurality of metal-oxide semiconductorfield-effect transistors comprises at least one N-MOSFET and/or oneP-MOSFET.